This project validates SN74-series TTL logic chips using an FPGA-driven test system. It combines digital logic design with a user-facing test interface, so the system can generate vectors, drive the chip under test, and display results clearly.
I implemented a custom VGA display controller, keyboard-based input handling, and FSM-based test pattern generation. The resulting interface can validate both combinational and sequential TTL circuits.
Technologies
- SystemVerilog
- FPGA
- Vivado
- VGA/HDMI